Hi @otso ,
sorry for the late response and thanks for your reply.
Yes, I was just logging instead of reading the FIFO buffer, and your explanation makes perfect sense. I should’ve tried to read the FIFO buffer before asking you this question about FIFO interrupts.
By the way, I followed your advice and edited my code according to this and, indeed, by reading the FIFO buffer every time an interrupt occurs, the buffer is cleared and this, in turn, let the interrupt timings to be the expected one.
Thanks again for your response