cpldfit: version K.39 Xilinx Inc. Fitter Report Design Name: ATM_top Date: 2-13-2011, 4:55PM Device Used: XC2C128-6-VQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 36 /128 ( 28%) 76 /448 ( 17%) 109 /320 ( 34%) 32 /128 ( 25%) 64 /80 ( 80%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO CTC CTR CTS CTE Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot FB1 6/16 31/40 19/56 6/10 0/1 0/1 0/1 1/1* FB2 0/16 0/40 0/56 0/10 0/1 0/1 0/1 0/1 FB3 10/16 31/40 23/56 10/11 0/1 0/1 0/1 1/1* FB4 10/16 20/40 16/56 10/11 0/1 0/1 0/1 0/1 FB5 0/16 0/40 0/56 0/10 0/1 0/1 0/1 0/1 FB6 0/16 0/40 0/56 0/ 9 0/1 0/1 0/1 0/1 FB7 8/16 25/40 16/56 8/10 0/1 0/1 0/1 0/1 FB8 2/16 2/40 2/56 2/ 9 0/1 0/1 0/1 0/1 ----- ------- ------- ----- --- --- --- --- Total 36/128 109/320 76/448 36/80 0/8 0/8 0/8 2/8 CTC - Control Term Clock CTR - Control Term Reset CTS - Control Term Set CTE - Control Term Output Enable * - Resource is exhausted ** Global Control Resources ** GCK GSR GTS Used/Tot Used/Tot Used/Tot 3/3 1/1 0/4 Signal 'ALE' mapped onto global clock net GCK0. Signal 'WE' mapped onto global clock net GCK1. Signal 'RD' mapped onto global clock net GCK2. Signal 'Rst' mapped onto global set/reset net GSR. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 24 24 | I/O : 56 70 Output : 28 28 | GCK/IO : 3 3 Bidirectional : 8 8 | GTS/IO : 4 4 GCK : 3 3 | GSR/IO : 1 1 GTS : 0 0 | CDR/IO : 0 1 GSR : 1 1 | DGE/IO : 0 1 ---- ---- Total 64 64 End of Mapped Resource Summary ************************** Errors and Warnings *************************** INFO:Cpld - Inferring BUFG constraint for signal 'ALE' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'RD' based upon the LOC constraint 'P27'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'WE' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. ************************* Summary of Mapped Logic ************************ ** 36 Outputs ** Signal Total Total Loc Pin Pin Pin I/O I/O Slew Reg Reg Init Name Pts Inps No. Type Use STD Style Rate Use State AD0_7<7> 4 21 FB1_6 9 I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<6> 4 21 FB1_11 8 I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<5> 4 21 FB1_12 7 I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<4> 4 21 FB1_13 6 I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<3> 4 21 FB1_15 4 GTS/I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<2> 4 21 FB1_16 3 GTS/I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<1> 4 21 FB3_2 2 GTS/I/O I/O LVTTL KPR FAST DEFF RESET AD0_7<0> 4 21 FB3_3 1 GTS/I/O I/O LVTTL KPR FAST DEFF RESET Leds1_0_7<0> 2 18 FB3_5 97 I/O O LVTTL FAST DEFF RESET Leds1_0_7<1> 2 18 FB3_6 96 I/O O LVTTL FAST DEFF RESET Leds1_0_7<2> 2 18 FB3_7 95 I/O O LVTTL FAST DEFF RESET Leds1_0_7<3> 2 18 FB3_11 94 I/O O LVTTL FAST DEFF RESET Leds1_0_7<4> 2 18 FB3_13 93 I/O O LVTTL FAST DEFF RESET Leds1_0_7<5> 2 18 FB3_14 92 I/O O LVTTL FAST DEFF RESET Leds1_0_7<6> 2 18 FB3_15 91 I/O O LVTTL FAST DEFF RESET Leds1_0_7<7> 2 18 FB3_16 90 I/O O LVTTL FAST DEFF RESET CE0 2 8 FB4_4 29 I/O O LVTTL FAST CE1 1 8 FB4_5 30 I/O O LVTTL FAST CE2 1 8 FB4_6 32 I/O O LVTTL FAST CE3 6 14 FB4_7 33 I/O O LVTTL FAST A0_7<0> 1 1 FB4_11 34 I/O O LVTTL FAST DFF RESET A0_7<1> 1 1 FB4_12 35 I/O O LVTTL FAST DFF RESET A0_7<2> 1 1 FB4_13 36 I/O O LVTTL FAST DFF RESET A0_7<3> 1 1 FB4_14 37 I/O O LVTTL FAST DFF RESET A0_7<4> 1 1 FB4_15 39 I/O O LVTTL FAST DFF RESET A0_7<5> 1 1 FB4_16 40 I/O O LVTTL FAST DFF RESET Leds2_0_7<7> 2 18 FB7_4 79 I/O O LVTTL FAST DEFF RESET Leds2_0_7<6> 2 18 FB7_5 80 I/O O LVTTL FAST DEFF RESET Leds2_0_7<5> 2 18 FB7_6 81 I/O O LVTTL FAST DEFF RESET Leds2_0_7<4> 2 18 FB7_11 82 I/O O LVTTL FAST DEFF RESET Leds2_0_7<3> 2 18 FB7_13 85 I/O O LVTTL FAST DEFF RESET Leds2_0_7<2> 2 18 FB7_14 86 I/O O LVTTL FAST DEFF RESET Leds2_0_7<1> 2 18 FB7_15 87 I/O O LVTTL FAST DEFF RESET Leds2_0_7<0> 2 18 FB7_16 89 I/O O LVTTL FAST DEFF RESET A0_7<7> 1 1 FB8_15 42 I/O O LVTTL FAST DFF RESET A0_7<6> 1 1 FB8_16 41 I/O O LVTTL FAST DFF RESET ** 36 Inputs ** Signal Loc Pin Pin Pin I/O I/O Name No. Type Use STD Style A8_15<3> FB1_1 13 I/O I LVTTL KPR A8_15<2> FB1_3 12 I/O I LVTTL KPR A8_15<1> FB1_4 11 I/O I LVTTL KPR A8_15<0> FB1_5 10 I/O I LVTTL KPR AD0_7<7> FB1_6 9 I/O I/O LVTTL KPR AD0_7<6> FB1_11 8 I/O I/O LVTTL KPR AD0_7<5> FB1_12 7 I/O I/O LVTTL KPR AD0_7<4> FB1_13 6 I/O I/O LVTTL KPR AD0_7<3> FB1_15 4 GTS/I/O I/O LVTTL KPR AD0_7<2> FB1_16 3 GTS/I/O I/O LVTTL KPR A8_15<4> FB2_2 14 I/O I LVTTL KPR A8_15<5> FB2_3 15 I/O I LVTTL KPR A8_15<6> FB2_4 16 I/O I LVTTL KPR A8_15<7> FB2_5 17 I/O I LVTTL KPR ALE FB2_13 22 GCK/I/O GCK LVTTL KPR WE FB2_14 23 GCK/I/O GCK/I LVTTL KPR RD FB2_16 27 GCK/I/O GCK/I LVTTL KPR AD0_7<1> FB3_2 2 GTS/I/O I/O LVTTL KPR AD0_7<0> FB3_3 1 GTS/I/O I/O LVTTL KPR Rst FB3_4 99 GSR/I/O GSR/I LVTTL KPR Dips2_0_7<0> FB5_2 66 I/O I LVTTL KPR Dips2_0_7<1> FB5_3 67 I/O I LVTTL KPR Dips2_0_7<2> FB5_5 68 I/O I LVTTL KPR Dips2_0_7<3> FB5_7 70 I/O I LVTTL KPR Dips2_0_7<4> FB5_11 71 I/O I LVTTL KPR Dips2_0_7<5> FB5_12 72 I/O I LVTTL KPR Dips2_0_7<6> FB5_13 73 I/O I LVTTL KPR Dips2_0_7<7> FB5_14 74 I/O I LVTTL KPR Dips1_0_7<7> FB6_1 64 I/O I LVTTL KPR Dips1_0_7<6> FB6_2 63 I/O I LVTTL KPR Dips1_0_7<5> FB6_3 61 I/O I LVTTL KPR Dips1_0_7<4> FB6_4 60 I/O I LVTTL KPR Dips1_0_7<3> FB6_5 59 I/O I LVTTL KPR Dips1_0_7<2> FB6_6 58 I/O I LVTTL KPR Dips1_0_7<1> FB6_12 56 I/O I LVTTL KPR Dips1_0_7<0> FB6_14 55 I/O I LVTTL KPR Legend: Pin No. - ~ - User Assigned I/O Style - OD - OpenDrain - PU - Pullup - KPR - Keeper - S - SchmittTrigger - DG - DataGate Reg Use - LATCH - Transparent latch - DFF - D-flip-flop - DEFF - D-flip-flop with clock enable - TFF - T-flip-flop - TDFF - Dual-edge-triggered T-flip-flop - DDFF - Dual-edge-triggered flip-flop - DDEFF - Dual-edge-triggered flip-flop with clock enable /S (after any above flop/latch type) indicates initial state is Set ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset VRF - Vref Pin No. - ~ - User Assigned *********************************** FB1 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 31/9 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 19/37 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB1_1 13 I/O I (unused) 0 FB1_2 (b) (unused) 0 FB1_3 12 I/O I (unused) 0 FB1_4 11 I/O I (unused) 0 FB1_5 10 I/O I AD0_7<7> 4 FB1_6 9 I/O I/O + (unused) 0 FB1_7 (b) (unused) 0 FB1_8 (b) (unused) 0 FB1_9 (b) (unused) 0 FB1_10 (b) AD0_7<6> 4 FB1_11 8 I/O I/O + AD0_7<5> 4 FB1_12 7 I/O I/O + AD0_7<4> 4 FB1_13 6 I/O I/O + (unused) 0 FB1_14 (b) AD0_7<3> 4 FB1_15 4 GTS/I/O I/O + AD0_7<2> 4 FB1_16 3 GTS/I/O I/O + Signals Used by Logic in Function Block 1: A0_7<0> 12: A8_15<3> 22: Dips1_0_7<7> 2: A0_7<1> 13: A8_15<4> 23: Dips2_0_7<2> 3: A0_7<2> 14: A8_15<5> 24: Dips2_0_7<3> 4: A0_7<3> 15: A8_15<6> 25: Dips2_0_7<4> 5: A0_7<4> 16: A8_15<7> 26: Dips2_0_7<5> 6: A0_7<5> 17: Dips1_0_7<2> 27: Dips2_0_7<6> 7: A0_7<6> 18: Dips1_0_7<3> 28: Dips2_0_7<7> 8: A0_7<7> 19: Dips1_0_7<4> 29: RD 9: A8_15<0> 20: Dips1_0_7<5> 30: Rst 10: A8_15<1> 21: Dips1_0_7<6> 31: WE 11: A8_15<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs AD0_7<7> XXXXXXXXXXXXXXXX.....X.....XXXX......... 21 AD0_7<6> XXXXXXXXXXXXXXXX....X.....X.XXX......... 21 AD0_7<5> XXXXXXXXXXXXXXXX...X.....X..XXX......... 21 AD0_7<4> XXXXXXXXXXXXXXXX..X.....X...XXX......... 21 AD0_7<3> XXXXXXXXXXXXXXXX.X.....X....XXX......... 21 AD0_7<2> XXXXXXXXXXXXXXXXX.....X.....XXX......... 21 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB2_1 (b) (unused) 0 FB2_2 14 I/O I (unused) 0 FB2_3 15 I/O I (unused) 0 FB2_4 16 I/O I (unused) 0 FB2_5 17 I/O I (unused) 0 FB2_6 18 I/O (unused) 0 FB2_7 (b) (unused) 0 FB2_8 (b) (unused) 0 FB2_9 (b) (unused) 0 FB2_10 (b) (unused) 0 FB2_11 19 I/O (unused) 0 FB2_12 (b) (unused) 0 FB2_13 22 GCK/I/O GCK (unused) 0 FB2_14 23 GCK/I/O GCK/I (unused) 0 FB2_15 24 CDR/I/O (unused) 0 FB2_16 27 GCK/I/O GCK/I *********************************** FB3 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 31/9 Number of function block control terms used/remaining: 1/3 Number of PLA product terms used/remaining: 23/33 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB3_1 (b) AD0_7<1> 4 FB3_2 2 GTS/I/O I/O + AD0_7<0> 4 FB3_3 1 GTS/I/O I/O + (unused) 0 FB3_4 99 GSR/I/O GSR/I Leds1_0_7<0> 2 FB3_5 97 I/O O Leds1_0_7<1> 2 FB3_6 96 I/O O Leds1_0_7<2> 2 FB3_7 95 I/O O (unused) 0 FB3_8 (b) (unused) 0 FB3_9 (b) (unused) 0 FB3_10 (b) Leds1_0_7<3> 2 FB3_11 94 I/O O (unused) 0 FB3_12 (b) Leds1_0_7<4> 2 FB3_13 93 I/O O Leds1_0_7<5> 2 FB3_14 92 I/O O Leds1_0_7<6> 2 FB3_15 91 I/O O Leds1_0_7<7> 2 FB3_16 90 I/O O Signals Used by Logic in Function Block 1: A0_7<0> 12: A8_15<3> 22: AD0_7<5>.PIN 2: A0_7<1> 13: A8_15<4> 23: AD0_7<6>.PIN 3: A0_7<2> 14: A8_15<5> 24: AD0_7<7>.PIN 4: A0_7<3> 15: A8_15<6> 25: Dips1_0_7<0> 5: A0_7<4> 16: A8_15<7> 26: Dips1_0_7<1> 6: A0_7<5> 17: AD0_7<0>.PIN 27: Dips2_0_7<0> 7: A0_7<6> 18: AD0_7<1>.PIN 28: Dips2_0_7<1> 8: A0_7<7> 19: AD0_7<2>.PIN 29: RD 9: A8_15<0> 20: AD0_7<3>.PIN 30: Rst 10: A8_15<1> 21: AD0_7<4>.PIN 31: WE 11: A8_15<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs AD0_7<1> XXXXXXXXXXXXXXXX.........X.XXXX......... 21 AD0_7<0> XXXXXXXXXXXXXXXX........X.X.XXX......... 21 Leds1_0_7<0> XXXXXXXXXXXXXXXXX...........X........... 18 Leds1_0_7<1> XXXXXXXXXXXXXXXX.X..........X........... 18 Leds1_0_7<2> XXXXXXXXXXXXXXXX..X.........X........... 18 Leds1_0_7<3> XXXXXXXXXXXXXXXX...X........X........... 18 Leds1_0_7<4> XXXXXXXXXXXXXXXX....X.......X........... 18 Leds1_0_7<5> XXXXXXXXXXXXXXXX.....X......X........... 18 Leds1_0_7<6> XXXXXXXXXXXXXXXX......X.....X........... 18 Leds1_0_7<7> XXXXXXXXXXXXXXXX.......X....X........... 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 20/20 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 16/40 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB4_1 28 DGE/I/O (unused) 0 FB4_2 (b) (unused) 0 FB4_3 (b) CE0 2 FB4_4 29 I/O O CE1 1 FB4_5 30 I/O O CE2 1 FB4_6 32 I/O O CE3 6 FB4_7 33 I/O O (unused) 0 FB4_8 (b) (unused) 0 FB4_9 (b) (unused) 0 FB4_10 (b) A0_7<0> 1 FB4_11 34 I/O O A0_7<1> 1 FB4_12 35 I/O O A0_7<2> 1 FB4_13 36 I/O O A0_7<3> 1 FB4_14 37 I/O O A0_7<4> 1 FB4_15 39 I/O O A0_7<5> 1 FB4_16 40 I/O O Signals Used by Logic in Function Block 1: A0_7<2> 8: A8_15<1> 15: AD0_7<0>.PIN 2: A0_7<3> 9: A8_15<2> 16: AD0_7<1>.PIN 3: A0_7<4> 10: A8_15<3> 17: AD0_7<2>.PIN 4: A0_7<5> 11: A8_15<4> 18: AD0_7<3>.PIN 5: A0_7<6> 12: A8_15<5> 19: AD0_7<4>.PIN 6: A0_7<7> 13: A8_15<6> 20: AD0_7<5>.PIN 7: A8_15<0> 14: A8_15<7> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs CE0 ......XXXXXXXX.......................... 8 CE1 ......XXXXXXXX.......................... 8 CE2 ......XXXXXXXX.......................... 8 CE3 XXXXXXXXXXXXXX.......................... 14 A0_7<0> ..............X......................... 1 A0_7<1> ...............X........................ 1 A0_7<2> ................X....................... 1 A0_7<3> .................X...................... 1 A0_7<4> ..................X..................... 1 A0_7<5> ...................X.................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB5_1 65 I/O (unused) 0 FB5_2 66 I/O I (unused) 0 FB5_3 67 I/O I (unused) 0 FB5_4 (b) (unused) 0 FB5_5 68 I/O I (unused) 0 FB5_6 (b) (unused) 0 FB5_7 70 I/O I (unused) 0 FB5_8 (b) (unused) 0 FB5_9 (b) (unused) 0 FB5_10 (b) (unused) 0 FB5_11 71 I/O I (unused) 0 FB5_12 72 I/O I (unused) 0 FB5_13 73 I/O I (unused) 0 FB5_14 74 I/O I (unused) 0 FB5_15 76 I/O (unused) 0 FB5_16 (b) *********************************** FB6 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 0/40 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 0/56 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB6_1 64 I/O I (unused) 0 FB6_2 63 I/O I (unused) 0 FB6_3 61 I/O I (unused) 0 FB6_4 60 I/O I (unused) 0 FB6_5 59 I/O I (unused) 0 FB6_6 58 I/O I (unused) 0 FB6_7 (b) (unused) 0 FB6_8 (b) (unused) 0 FB6_9 (b) (unused) 0 FB6_10 (b) (unused) 0 FB6_11 (b) (unused) 0 FB6_12 56 I/O I (unused) 0 FB6_13 (b) (unused) 0 FB6_14 55 I/O I (unused) 0 FB6_15 (b) (unused) 0 FB6_16 54 I/O *********************************** FB7 *********************************** This function block is part of I/O Bank number: 2 Number of function block inputs used/remaining: 25/15 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 16/40 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB7_1 77 I/O (unused) 0 FB7_2 78 I/O (unused) 0 FB7_3 (b) Leds2_0_7<7> 2 FB7_4 79 I/O O Leds2_0_7<6> 2 FB7_5 80 I/O O Leds2_0_7<5> 2 FB7_6 81 I/O O (unused) 0 FB7_7 (b) (unused) 0 FB7_8 (b) (unused) 0 FB7_9 (b) (unused) 0 FB7_10 (b) Leds2_0_7<4> 2 FB7_11 82 I/O O (unused) 0 FB7_12 (b) Leds2_0_7<3> 2 FB7_13 85 I/O O Leds2_0_7<2> 2 FB7_14 86 I/O O Leds2_0_7<1> 2 FB7_15 87 I/O O Leds2_0_7<0> 2 FB7_16 89 I/O O Signals Used by Logic in Function Block 1: A0_7<0> 10: A8_15<1> 18: AD0_7<1>.PIN 2: A0_7<1> 11: A8_15<2> 19: AD0_7<2>.PIN 3: A0_7<2> 12: A8_15<3> 20: AD0_7<3>.PIN 4: A0_7<3> 13: A8_15<4> 21: AD0_7<4>.PIN 5: A0_7<4> 14: A8_15<5> 22: AD0_7<5>.PIN 6: A0_7<5> 15: A8_15<6> 23: AD0_7<6>.PIN 7: A0_7<6> 16: A8_15<7> 24: AD0_7<7>.PIN 8: A0_7<7> 17: AD0_7<0>.PIN 25: RD 9: A8_15<0> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs Leds2_0_7<7> XXXXXXXXXXXXXXXX.......XX............... 18 Leds2_0_7<6> XXXXXXXXXXXXXXXX......X.X............... 18 Leds2_0_7<5> XXXXXXXXXXXXXXXX.....X..X............... 18 Leds2_0_7<4> XXXXXXXXXXXXXXXX....X...X............... 18 Leds2_0_7<3> XXXXXXXXXXXXXXXX...X....X............... 18 Leds2_0_7<2> XXXXXXXXXXXXXXXX..X.....X............... 18 Leds2_0_7<1> XXXXXXXXXXXXXXXX.X......X............... 18 Leds2_0_7<0> XXXXXXXXXXXXXXXXX.......X............... 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** This function block is part of I/O Bank number: 1 Number of function block inputs used/remaining: 2/38 Number of function block control terms used/remaining: 0/4 Number of PLA product terms used/remaining: 2/54 Signal Total Loc Pin Pin Pin CTC CTR CTS CTE Name Pt No. Type Use (unused) 0 FB8_1 (b) (unused) 0 FB8_2 53 I/O (unused) 0 FB8_3 52 I/O (unused) 0 FB8_4 50 I/O (unused) 0 FB8_5 (b) (unused) 0 FB8_6 49 I/O (unused) 0 FB8_7 (b) (unused) 0 FB8_8 (b) (unused) 0 FB8_9 (b) (unused) 0 FB8_10 (b) (unused) 0 FB8_11 (b) (unused) 0 FB8_12 46 I/O (unused) 0 FB8_13 44 I/O (unused) 0 FB8_14 43 I/O A0_7<7> 1 FB8_15 42 I/O O A0_7<6> 1 FB8_16 41 I/O O Signals Used by Logic in Function Block 1: AD0_7<6>.PIN 2: AD0_7<7>.PIN Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs A0_7<7> .X...................................... 1 A0_7<6> X....................................... 1 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** FDCPE_A0_70: FDCPE port map (A0_7(0),AD0_7(0).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_71: FDCPE port map (A0_7(1),AD0_7(1).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_72: FDCPE port map (A0_7(2),AD0_7(2).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_73: FDCPE port map (A0_7(3),AD0_7(3).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_74: FDCPE port map (A0_7(4),AD0_7(4).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_75: FDCPE port map (A0_7(5),AD0_7(5).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_76: FDCPE port map (A0_7(6),AD0_7(6).PIN,ALE,NOT Rst,'0','1'); FDCPE_A0_77: FDCPE port map (A0_7(7),AD0_7(7).PIN,ALE,NOT Rst,'0','1'); FDCPE_AD0_70: FDCPE port map (AD0_7_I(0),AD0_7(0),RD,NOT Rst,'0',AD0_7_CE(0)); AD0_7(0) <= ((A0_7(0) AND Dips2_0_7(0)) OR (NOT A0_7(0) AND Dips1_0_7(0))); AD0_7(0) <= AD0_7_I(0) when AD0_7_OE(0) = '1' else 'Z'; AD0_7_OE(0) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(0) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_71: FDCPE port map (AD0_7_I(1),AD0_7(1),RD,NOT Rst,'0',AD0_7_CE(1)); AD0_7(1) <= ((A0_7(0) AND Dips2_0_7(1)) OR (NOT A0_7(0) AND Dips1_0_7(1))); AD0_7(1) <= AD0_7_I(1) when AD0_7_OE(1) = '1' else 'Z'; AD0_7_OE(1) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(1) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_72: FDCPE port map (AD0_7_I(2),AD0_7(2),RD,NOT Rst,'0',AD0_7_CE(2)); AD0_7(2) <= ((A0_7(0) AND Dips2_0_7(2)) OR (NOT A0_7(0) AND Dips1_0_7(2))); AD0_7(2) <= AD0_7_I(2) when AD0_7_OE(2) = '1' else 'Z'; AD0_7_OE(2) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(2) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_73: FDCPE port map (AD0_7_I(3),AD0_7(3),RD,NOT Rst,'0',AD0_7_CE(3)); AD0_7(3) <= ((A0_7(0) AND Dips2_0_7(3)) OR (NOT A0_7(0) AND Dips1_0_7(3))); AD0_7(3) <= AD0_7_I(3) when AD0_7_OE(3) = '1' else 'Z'; AD0_7_OE(3) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(3) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_74: FDCPE port map (AD0_7_I(4),AD0_7(4),RD,NOT Rst,'0',AD0_7_CE(4)); AD0_7(4) <= ((A0_7(0) AND Dips2_0_7(4)) OR (NOT A0_7(0) AND Dips1_0_7(4))); AD0_7(4) <= AD0_7_I(4) when AD0_7_OE(4) = '1' else 'Z'; AD0_7_OE(4) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(4) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_75: FDCPE port map (AD0_7_I(5),AD0_7(5),RD,NOT Rst,'0',AD0_7_CE(5)); AD0_7(5) <= ((A0_7(0) AND Dips2_0_7(5)) OR (NOT A0_7(0) AND Dips1_0_7(5))); AD0_7(5) <= AD0_7_I(5) when AD0_7_OE(5) = '1' else 'Z'; AD0_7_OE(5) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(5) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_76: FDCPE port map (AD0_7_I(6),AD0_7(6),RD,NOT Rst,'0',AD0_7_CE(6)); AD0_7(6) <= ((A0_7(0) AND Dips2_0_7(6)) OR (NOT A0_7(0) AND Dips1_0_7(6))); AD0_7(6) <= AD0_7_I(6) when AD0_7_OE(6) = '1' else 'Z'; AD0_7_OE(6) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(6) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); FDCPE_AD0_77: FDCPE port map (AD0_7_I(7),AD0_7(7),RD,NOT Rst,'0',AD0_7_CE(7)); AD0_7(7) <= ((A0_7(0) AND Dips2_0_7(7)) OR (NOT A0_7(0) AND Dips1_0_7(7))); AD0_7(7) <= AD0_7_I(7) when AD0_7_OE(7) = '1' else 'Z'; AD0_7_OE(7) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND RD AND Rst); AD0_7_CE(7) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT WE); CE0 <= NOT (((A8_15(7) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0)) OR (A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0)))); CE1 <= (A8_15(7) AND NOT A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0)); CE2 <= (NOT A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0)); CE3 <= ((A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(2)) OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(3)) OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(4)) OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(5)) OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(6)) OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(7))); FDCPE_Leds1_0_70: FDCPE port map (Leds1_0_7(0),AD0_7(0).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(0)); Leds1_0_7_CE(0) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_71: FDCPE port map (Leds1_0_7(1),AD0_7(1).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(1)); Leds1_0_7_CE(1) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_72: FDCPE port map (Leds1_0_7(2),AD0_7(2).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(2)); Leds1_0_7_CE(2) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_73: FDCPE port map (Leds1_0_7(3),AD0_7(3).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(3)); Leds1_0_7_CE(3) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_74: FDCPE port map (Leds1_0_7(4),AD0_7(4).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(4)); Leds1_0_7_CE(4) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_75: FDCPE port map (Leds1_0_7(5),AD0_7(5).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(5)); Leds1_0_7_CE(5) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_76: FDCPE port map (Leds1_0_7(6),AD0_7(6).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(6)); Leds1_0_7_CE(6) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds1_0_77: FDCPE port map (Leds1_0_7(7),AD0_7(7).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(7)); Leds1_0_7_CE(7) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_70: FDCPE port map (Leds2_0_7(0),AD0_7(0).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(0)); Leds2_0_7_CE(0) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_71: FDCPE port map (Leds2_0_7(1),AD0_7(1).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(1)); Leds2_0_7_CE(1) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_72: FDCPE port map (Leds2_0_7(2),AD0_7(2).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(2)); Leds2_0_7_CE(2) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_73: FDCPE port map (Leds2_0_7(3),AD0_7(3).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(3)); Leds2_0_7_CE(3) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_74: FDCPE port map (Leds2_0_7(4),AD0_7(4).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(4)); Leds2_0_7_CE(4) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_75: FDCPE port map (Leds2_0_7(5),AD0_7(5).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(5)); Leds2_0_7_CE(5) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_76: FDCPE port map (Leds2_0_7(6),AD0_7(6).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(6)); Leds2_0_7_CE(6) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); FDCPE_Leds2_0_77: FDCPE port map (Leds2_0_7(7),AD0_7(7).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(7)); Leds2_0_7_CE(7) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND A0_7(7) AND NOT RD); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FDDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); FTDCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC2C128-6-VQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC2C128-6-VQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 AD0_7<0> 51 VCCIO-3.3 2 AD0_7<1> 52 KPR 3 AD0_7<2> 53 KPR 4 AD0_7<3> 54 KPR 5 VCCAUX 55 Dips1_0_7<0> 6 AD0_7<4> 56 Dips1_0_7<1> 7 AD0_7<5> 57 VCC 8 AD0_7<6> 58 Dips1_0_7<2> 9 AD0_7<7> 59 Dips1_0_7<3> 10 A8_15<0> 60 Dips1_0_7<4> 11 A8_15<1> 61 Dips1_0_7<5> 12 A8_15<2> 62 GND 13 A8_15<3> 63 Dips1_0_7<6> 14 A8_15<4> 64 Dips1_0_7<7> 15 A8_15<5> 65 KPR 16 A8_15<6> 66 Dips2_0_7<0> 17 A8_15<7> 67 Dips2_0_7<1> 18 KPR 68 Dips2_0_7<2> 19 KPR 69 GND 20 VCCIO-3.3 70 Dips2_0_7<3> 21 GND 71 Dips2_0_7<4> 22 ALE 72 Dips2_0_7<5> 23 WE 73 Dips2_0_7<6> 24 KPR 74 Dips2_0_7<7> 25 GND 75 GND 26 VCC 76 KPR 27 RD 77 KPR 28 KPR 78 KPR 29 CE0 79 Leds2_0_7<7> 30 CE1 80 Leds2_0_7<6> 31 GND 81 Leds2_0_7<5> 32 CE2 82 Leds2_0_7<4> 33 CE3 83 TDO 34 A0_7<0> 84 GND 35 A0_7<1> 85 Leds2_0_7<3> 36 A0_7<2> 86 Leds2_0_7<2> 37 A0_7<3> 87 Leds2_0_7<1> 38 VCCIO-3.3 88 VCCIO-3.3 39 A0_7<4> 89 Leds2_0_7<0> 40 A0_7<5> 90 Leds1_0_7<7> 41 A0_7<6> 91 Leds1_0_7<6> 42 A0_7<7> 92 Leds1_0_7<5> 43 KPR 93 Leds1_0_7<4> 44 KPR 94 Leds1_0_7<3> 45 TDI 95 Leds1_0_7<2> 46 KPR 96 Leds1_0_7<1> 47 TMS 97 Leds1_0_7<0> 48 TCK 98 VCCIO-3.3 49 KPR 99 Rst 50 KPR 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin KPR = Unused I/O with weak keeper (leave unconnected) WPU = Unused I/O with weak pull up (leave unconnected) TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin VCCAUX = Power supply for JTAG pins VCCIO-3.3 = I/O supply voltage for LVTTL, LVCMOS33, SSTL3_I VCCIO-2.5 = I/O supply voltage for LVCMOS25, SSTL2_I VCCIO-1.8 = I/O supply voltage for LVCMOS18 VCCIO-1.5 = I/O supply voltage for LVCMOS15, HSTL_I VREF = Reference voltage for indicated input standard *VREF = Reference voltage pin selected by software GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc2c128-6-VQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Set Unused I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Enable Input Registers : ON Function Block Fan-in Limit : 38 Use DATA_GATE Attribute : ON Set Tristate Outputs to Termination Mode : KEEPER Default Voltage Standard for All Outputs : LVCMOS33 Input Limit : 32 Pterm Limit : 28