Equations

********** Mapped Logic **********
FDCPE_A0_70: FDCPE port map (A0_7(0),AD0_7(0).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_71: FDCPE port map (A0_7(1),AD0_7(1).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_72: FDCPE port map (A0_7(2),AD0_7(2).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_73: FDCPE port map (A0_7(3),AD0_7(3).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_74: FDCPE port map (A0_7(4),AD0_7(4).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_75: FDCPE port map (A0_7(5),AD0_7(5).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_76: FDCPE port map (A0_7(6),AD0_7(6).PIN,ALE,NOT Rst,'0','1');
FDCPE_A0_77: FDCPE port map (A0_7(7),AD0_7(7).PIN,ALE,NOT Rst,'0','1');
FDCPE_AD0_70: FDCPE port map (AD0_7_I(0),AD0_7(0),RD,NOT Rst,'0',AD0_7_CE(0));
     AD0_7(0) <= ((A0_7(0) AND Dips2_0_7(0))
      OR (NOT A0_7(0) AND Dips1_0_7(0)));
     AD0_7(0) <= AD0_7_I(0) when AD0_7_OE(0) = '1' else 'Z';
     AD0_7_OE(0) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(0) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_71: FDCPE port map (AD0_7_I(1),AD0_7(1),RD,NOT Rst,'0',AD0_7_CE(1));
     AD0_7(1) <= ((A0_7(0) AND Dips2_0_7(1))
      OR (NOT A0_7(0) AND Dips1_0_7(1)));
     AD0_7(1) <= AD0_7_I(1) when AD0_7_OE(1) = '1' else 'Z';
     AD0_7_OE(1) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(1) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_72: FDCPE port map (AD0_7_I(2),AD0_7(2),RD,NOT Rst,'0',AD0_7_CE(2));
     AD0_7(2) <= ((A0_7(0) AND Dips2_0_7(2))
      OR (NOT A0_7(0) AND Dips1_0_7(2)));
     AD0_7(2) <= AD0_7_I(2) when AD0_7_OE(2) = '1' else 'Z';
     AD0_7_OE(2) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(2) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_73: FDCPE port map (AD0_7_I(3),AD0_7(3),RD,NOT Rst,'0',AD0_7_CE(3));
     AD0_7(3) <= ((A0_7(0) AND Dips2_0_7(3))
      OR (NOT A0_7(0) AND Dips1_0_7(3)));
     AD0_7(3) <= AD0_7_I(3) when AD0_7_OE(3) = '1' else 'Z';
     AD0_7_OE(3) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(3) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_74: FDCPE port map (AD0_7_I(4),AD0_7(4),RD,NOT Rst,'0',AD0_7_CE(4));
     AD0_7(4) <= ((A0_7(0) AND Dips2_0_7(4))
      OR (NOT A0_7(0) AND Dips1_0_7(4)));
     AD0_7(4) <= AD0_7_I(4) when AD0_7_OE(4) = '1' else 'Z';
     AD0_7_OE(4) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(4) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_75: FDCPE port map (AD0_7_I(5),AD0_7(5),RD,NOT Rst,'0',AD0_7_CE(5));
     AD0_7(5) <= ((A0_7(0) AND Dips2_0_7(5))
      OR (NOT A0_7(0) AND Dips1_0_7(5)));
     AD0_7(5) <= AD0_7_I(5) when AD0_7_OE(5) = '1' else 'Z';
     AD0_7_OE(5) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(5) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_76: FDCPE port map (AD0_7_I(6),AD0_7(6),RD,NOT Rst,'0',AD0_7_CE(6));
     AD0_7(6) <= ((A0_7(0) AND Dips2_0_7(6))
      OR (NOT A0_7(0) AND Dips1_0_7(6)));
     AD0_7(6) <= AD0_7_I(6) when AD0_7_OE(6) = '1' else 'Z';
     AD0_7_OE(6) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(6) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
FDCPE_AD0_77: FDCPE port map (AD0_7_I(7),AD0_7(7),RD,NOT Rst,'0',AD0_7_CE(7));
     AD0_7(7) <= ((A0_7(0) AND Dips2_0_7(7))
      OR (NOT A0_7(0) AND Dips1_0_7(7)));
     AD0_7(7) <= AD0_7_I(7) when AD0_7_OE(7) = '1' else 'Z';
     AD0_7_OE(7) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND RD AND Rst);
     AD0_7_CE(7) <= (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(1) AND
      A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND A0_7(6) AND
      A0_7(7) AND NOT WE);
CE0 <= NOT (((A8_15(7) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND
      A8_15(2) AND A8_15(1) AND A8_15(0))
      OR (A8_15(6) AND A8_15(5) AND A8_15(4) AND A8_15(3) AND
      A8_15(2) AND A8_15(1) AND A8_15(0))));
CE1 <= (A8_15(7) AND NOT A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0));
CE2 <= (NOT A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0));
CE3 <= ((A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(2))
      OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(3))
      OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(4))
      OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(5))
      OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(6))
      OR (A8_15(7) AND A8_15(6) AND A8_15(5) AND A8_15(4) AND
      A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND NOT A0_7(7)));
FDCPE_Leds1_0_70: FDCPE port map (Leds1_0_7(0),AD0_7(0).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(0));
     Leds1_0_7_CE(0) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_71: FDCPE port map (Leds1_0_7(1),AD0_7(1).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(1));
     Leds1_0_7_CE(1) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_72: FDCPE port map (Leds1_0_7(2),AD0_7(2).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(2));
     Leds1_0_7_CE(2) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_73: FDCPE port map (Leds1_0_7(3),AD0_7(3).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(3));
     Leds1_0_7_CE(3) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_74: FDCPE port map (Leds1_0_7(4),AD0_7(4).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(4));
     Leds1_0_7_CE(4) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_75: FDCPE port map (Leds1_0_7(5),AD0_7(5).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(5));
     Leds1_0_7_CE(5) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_76: FDCPE port map (Leds1_0_7(6),AD0_7(6).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(6));
     Leds1_0_7_CE(6) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds1_0_77: FDCPE port map (Leds1_0_7(7),AD0_7(7).PIN,WE,NOT Rst,'0',Leds1_0_7_CE(7));
     Leds1_0_7_CE(7) <= (NOT A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_70: FDCPE port map (Leds2_0_7(0),AD0_7(0).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(0));
     Leds2_0_7_CE(0) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_71: FDCPE port map (Leds2_0_7(1),AD0_7(1).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(1));
     Leds2_0_7_CE(1) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_72: FDCPE port map (Leds2_0_7(2),AD0_7(2).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(2));
     Leds2_0_7_CE(2) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_73: FDCPE port map (Leds2_0_7(3),AD0_7(3).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(3));
     Leds2_0_7_CE(3) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_74: FDCPE port map (Leds2_0_7(4),AD0_7(4).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(4));
     Leds2_0_7_CE(4) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_75: FDCPE port map (Leds2_0_7(5),AD0_7(5).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(5));
     Leds2_0_7_CE(5) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_76: FDCPE port map (Leds2_0_7(6),AD0_7(6).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(6));
     Leds2_0_7_CE(6) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
FDCPE_Leds2_0_77: FDCPE port map (Leds2_0_7(7),AD0_7(7).PIN,WE,NOT Rst,'0',Leds2_0_7_CE(7));
     Leds2_0_7_CE(7) <= (A0_7(0) AND A8_15(7) AND A8_15(6) AND A8_15(5) AND
      A8_15(4) AND A8_15(3) AND A8_15(2) AND A8_15(1) AND A8_15(0) AND
      A0_7(1) AND A0_7(2) AND A0_7(3) AND A0_7(4) AND A0_7(5) AND
      A0_7(6) AND A0_7(7) AND NOT RD);
Register Legend:
      FDCPE (Q,D,C,CLR,PRE,CE);
      FDDCPE (Q,D,C,CLR,PRE,CE);
      FTCPE (Q,D,C,CLR,PRE,CE);
      FTDCPE (Q,D,C,CLR,PRE,CE);
      LDCP (Q,D,G,CLR,PRE);