Timing Report

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Design Name ATM_top
Device, Speed (SpeedFile Version) XC2C128, -6 (14.0 Advance Product Specification)
Date Created Sun Feb 13 16:55:37 2011
Created By Timing Report Generator: version K.39
Copyright Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 2.200 ns.
Max. Clock Frequency (fSYSTEM) 454.545 MHz.
Limited by Clock Pulse Width for WE
Pad to Pad Delay (tPD) 8.700 ns.
Setup to Clock at the Pad (tSU) 3.100 ns.
Clock Pad to Output Pad Delay (tCO) 10.400 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
AUTO_TS_F2F 0.0 4.8 192 192
AUTO_TS_P2P 0.0 10.4 153 153
AUTO_TS_P2F 0.0 5.1 259 259
AUTO_TS_F2P 0.0 8.4 94 94


Constraint: TS1000

Description: PERIOD:PERIOD_WE:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_RD:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_ALE:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A0_7<0>.Q to Leds1_0_7<0>.CE 0.000 4.800 -4.800
A0_7<0>.Q to Leds1_0_7<1>.CE 0.000 4.800 -4.800
A0_7<0>.Q to Leds1_0_7<2>.CE 0.000 4.800 -4.800


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
ALE to AD0_7<0> 0.000 10.400 -10.400
ALE to AD0_7<1> 0.000 10.400 -10.400
ALE to AD0_7<2> 0.000 10.400 -10.400


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A8_15<0> to AD0_7<0>.CE 0.000 5.100 -5.100
A8_15<0> to AD0_7<1>.CE 0.000 5.100 -5.100
A8_15<0> to AD0_7<2>.CE 0.000 5.100 -5.100


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A0_7<1>.Q to AD0_7<0> 0.000 8.400 -8.400
A0_7<1>.Q to AD0_7<1> 0.000 8.400 -8.400
A0_7<1>.Q to AD0_7<2> 0.000 8.400 -8.400



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
WE 454.545 Limited by Clock Pulse Width for WE
RD 454.545 Limited by Clock Pulse Width for RD
ALE 454.545 Limited by Clock Pulse Width for ALE

Setup/Hold Times for Clocks

Setup/Hold Times for Clock WE
Source Pad Setup to clk (edge) Hold to clk (edge)
A8_15<0> 3.100 0.000
A8_15<1> 3.100 0.000
A8_15<2> 3.100 0.000
A8_15<3> 3.100 0.000
A8_15<4> 3.100 0.000
A8_15<5> 3.100 0.000
A8_15<6> 3.100 0.000
A8_15<7> 3.100 0.000
AD0_7<0> 2.700 0.000
AD0_7<1> 2.700 0.000
AD0_7<2> 2.700 0.000
AD0_7<3> 2.700 0.000
AD0_7<4> 2.700 0.000
AD0_7<5> 2.700 0.000
AD0_7<6> 2.700 0.000
AD0_7<7> 2.700 0.000
RD 3.100 0.000

Setup/Hold Times for Clock RD
Source Pad Setup to clk (edge) Hold to clk (edge)
A8_15<0> 3.100 0.000
A8_15<1> 3.100 0.000
A8_15<2> 3.100 0.000
A8_15<3> 3.100 0.000
A8_15<4> 3.100 0.000
A8_15<5> 3.100 0.000
A8_15<6> 3.100 0.000
A8_15<7> 3.100 0.000
Dips1_0_7<0> 2.700 0.000
Dips1_0_7<1> 2.700 0.000
Dips1_0_7<2> 2.700 0.000
Dips1_0_7<3> 2.700 0.000
Dips1_0_7<4> 2.700 0.000
Dips1_0_7<5> 2.700 0.000
Dips1_0_7<6> 2.700 0.000
Dips1_0_7<7> 2.700 0.000
Dips2_0_7<0> 2.700 0.000
Dips2_0_7<1> 2.700 0.000
Dips2_0_7<2> 2.700 0.000
Dips2_0_7<3> 2.700 0.000
Dips2_0_7<4> 2.700 0.000
Dips2_0_7<5> 2.700 0.000
Dips2_0_7<6> 2.700 0.000
Dips2_0_7<7> 2.700 0.000
WE 3.100 0.000

Setup/Hold Times for Clock ALE
Source Pad Setup to clk (edge) Hold to clk (edge)
AD0_7<0> 2.400 0.000
AD0_7<1> 2.400 0.000
AD0_7<2> 2.400 0.000
AD0_7<3> 2.400 0.000
AD0_7<4> 2.400 0.000
AD0_7<5> 2.400 0.000
AD0_7<6> 2.400 0.000
AD0_7<7> 2.400 0.000


Clock to Pad Timing

Clock WE to Pad
Destination Pad Clock (edge) to Pad
Leds1_0_7<0> 5.900
Leds1_0_7<1> 5.900
Leds1_0_7<2> 5.900
Leds1_0_7<3> 5.900
Leds1_0_7<4> 5.900
Leds1_0_7<5> 5.900
Leds1_0_7<6> 5.900
Leds1_0_7<7> 5.900
Leds2_0_7<0> 5.900
Leds2_0_7<1> 5.900
Leds2_0_7<2> 5.900
Leds2_0_7<3> 5.900
Leds2_0_7<4> 5.900
Leds2_0_7<5> 5.900
Leds2_0_7<6> 5.900
Leds2_0_7<7> 5.900

Clock RD to Pad
Destination Pad Clock (edge) to Pad
AD0_7<0> 5.900
AD0_7<1> 5.900
AD0_7<2> 5.900
AD0_7<3> 5.900
AD0_7<4> 5.900
AD0_7<5> 5.900
AD0_7<6> 5.900
AD0_7<7> 5.900

Clock ALE to Pad
Destination Pad Clock (edge) to Pad
AD0_7<0> 10.400
AD0_7<1> 10.400
AD0_7<2> 10.400
AD0_7<3> 10.400
AD0_7<4> 10.400
AD0_7<5> 10.400
AD0_7<6> 10.400
AD0_7<7> 10.400
CE3 9.400
A0_7<0> 5.900
A0_7<1> 5.900
A0_7<2> 5.900
A0_7<3> 5.900
A0_7<4> 5.900
A0_7<5> 5.900
A0_7<6> 5.900
A0_7<7> 5.900


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
A8_15<0> AD0_7<0> 8.700
A8_15<0> AD0_7<1> 8.700
A8_15<0> AD0_7<2> 8.700
A8_15<0> AD0_7<3> 8.700
A8_15<0> AD0_7<4> 8.700
A8_15<0> AD0_7<5> 8.700
A8_15<0> AD0_7<6> 8.700
A8_15<0> AD0_7<7> 8.700
A8_15<1> AD0_7<0> 8.700
A8_15<1> AD0_7<1> 8.700
A8_15<1> AD0_7<2> 8.700
A8_15<1> AD0_7<3> 8.700
A8_15<1> AD0_7<4> 8.700
A8_15<1> AD0_7<5> 8.700
A8_15<1> AD0_7<6> 8.700
A8_15<1> AD0_7<7> 8.700
A8_15<2> AD0_7<0> 8.700
A8_15<2> AD0_7<1> 8.700
A8_15<2> AD0_7<2> 8.700
A8_15<2> AD0_7<3> 8.700
A8_15<2> AD0_7<4> 8.700
A8_15<2> AD0_7<5> 8.700
A8_15<2> AD0_7<6> 8.700
A8_15<2> AD0_7<7> 8.700
A8_15<3> AD0_7<0> 8.700
A8_15<3> AD0_7<1> 8.700
A8_15<3> AD0_7<2> 8.700
A8_15<3> AD0_7<3> 8.700
A8_15<3> AD0_7<4> 8.700
A8_15<3> AD0_7<5> 8.700
A8_15<3> AD0_7<6> 8.700
A8_15<3> AD0_7<7> 8.700
A8_15<4> AD0_7<0> 8.700
A8_15<4> AD0_7<1> 8.700
A8_15<4> AD0_7<2> 8.700
A8_15<4> AD0_7<3> 8.700
A8_15<4> AD0_7<4> 8.700
A8_15<4> AD0_7<5> 8.700
A8_15<4> AD0_7<6> 8.700
A8_15<4> AD0_7<7> 8.700
A8_15<5> AD0_7<0> 8.700
A8_15<5> AD0_7<1> 8.700
A8_15<5> AD0_7<2> 8.700
A8_15<5> AD0_7<3> 8.700
A8_15<5> AD0_7<4> 8.700
A8_15<5> AD0_7<5> 8.700
A8_15<5> AD0_7<6> 8.700
A8_15<5> AD0_7<7> 8.700
A8_15<6> AD0_7<0> 8.700
A8_15<6> AD0_7<1> 8.700
A8_15<6> AD0_7<2> 8.700
A8_15<6> AD0_7<3> 8.700
A8_15<6> AD0_7<4> 8.700
A8_15<6> AD0_7<5> 8.700
A8_15<6> AD0_7<6> 8.700
A8_15<6> AD0_7<7> 8.700
A8_15<7> AD0_7<0> 8.700
A8_15<7> AD0_7<1> 8.700
A8_15<7> AD0_7<2> 8.700
A8_15<7> AD0_7<3> 8.700
A8_15<7> AD0_7<4> 8.700
A8_15<7> AD0_7<5> 8.700
A8_15<7> AD0_7<6> 8.700
A8_15<7> AD0_7<7> 8.700
RD AD0_7<0> 8.700
RD AD0_7<1> 8.700
RD AD0_7<2> 8.700
RD AD0_7<3> 8.700
RD AD0_7<4> 8.700
RD AD0_7<5> 8.700
RD AD0_7<6> 8.700
RD AD0_7<7> 8.700
Rst AD0_7<0> 8.700
Rst AD0_7<1> 8.700
Rst AD0_7<2> 8.700
Rst AD0_7<3> 8.700
Rst AD0_7<4> 8.700
Rst AD0_7<5> 8.700
Rst AD0_7<6> 8.700
Rst AD0_7<7> 8.700
A8_15<0> CE0 7.700
A8_15<0> CE3 7.700
A8_15<1> CE0 7.700
A8_15<1> CE3 7.700
A8_15<2> CE0 7.700
A8_15<2> CE3 7.700
A8_15<3> CE0 7.700
A8_15<3> CE3 7.700
A8_15<4> CE0 7.700
A8_15<4> CE3 7.700
A8_15<5> CE0 7.700
A8_15<5> CE3 7.700
A8_15<6> CE0 7.700
A8_15<6> CE3 7.700
A8_15<7> CE0 7.700
A8_15<7> CE3 7.700
A8_15<0> CE1 7.400
A8_15<0> CE2 7.400
A8_15<1> CE1 7.400
A8_15<1> CE2 7.400
A8_15<2> CE1 7.400
A8_15<2> CE2 7.400
A8_15<3> CE1 7.400
A8_15<3> CE2 7.400
A8_15<4> CE1 7.400
A8_15<4> CE2 7.400
A8_15<5> CE1 7.400
A8_15<5> CE2 7.400
A8_15<6> CE1 7.400
A8_15<6> CE2 7.400
A8_15<7> CE1 7.400
A8_15<7> CE2 7.400



Number of paths analyzed: 698
Number of Timing errors: 698
Analysis Completed: Sun Feb 13 16:55:37 2011